Integrated circuits (“ICs”) are incorporated into many electronic devices. IC packaging has evolved, such that multiple ICs may be vertically stacked in so-called three-dimensional (“3D”) packages in order to save horizontal area on a printed circuit board (“PCB”). 3D IC packages include the use of through substrate vias (TSV), also referred to as through-silicon-vias, in the case of silicon-based dies. The inclusion of TSV increases the complexity of semiconductor fabrication and packaging. For example, TSV-to-TSV coupling is an additional noise source for 3D IC packages.
The design process for a new IC includes several steps by using, for example, automated electronic design automation (“EDA”) tools. The design process can include (1) determining an initial design of the IC and (2) generating a layout of the design. During the initial design, a user (of the EDA tool) or designer can identify a set of functions to include in the design, along with their standard delays. The user can also use computer implemented tools to perform functional simulation to ensure that the design can perform a pre-simulation process. If the design meets circuit performance requirements during the pre-simulation process, the user can then initiate floorplan and layout (“place and route”) phases to generate an actual layout. Following the layout process, the user can verify the design by using the EDA tools to perform design rule checks (“DRC”), layout versus schematic (“LVS”) checks, and RC extraction. The RC extraction tool takes into account the layout of the conductive (e.g., metal) lines of the interconnect layers generated by the router and computes parasitic resistance and capacitance elements associated with each conductive line. Then a post-simulation process verifies circuit performance and timing.
When considering a coupling between at least two TSVs during, for example, a small scale timing analysis, a network spice model can be used to simulate the coupling effect. When conducing, for example, a full-chip timing analysis, a static timing analysis (“STA”) tool can be used. However, the STA tool facilitates a more restricted network style, wherein the coupling capacitance that is between different networks is considered. As such, the STA tool is unable to support a full-chip timing analysis.